The testing scheme for vhd2vl is sensitive to subtle shifts in iverilog's parenthesization choices, meaning that the golden test outputs require constant maintenance. The patch previously applied in order to deal with this situation is no longer sufficient, so a patch which is sufficient has been added. Also, the `buildTargets` and `checkTarget` attributes have been set, so future benign failures of this sort can be dealt with through `doCheck=false` in a pinch.main
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@ -0,0 +1,35 @@ |
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--- a/translated_examples/fifo.v 1970-01-01 00:00:01.000000000 +0000
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+++ a/temp/verilog/fifo.v 2022-05-11 03:44:43.173604945 +0000
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@@ -107,7 +107,7 @@
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//--- Read address counter --------------
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//---------------------------------------
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assign add_RD_CE = (iempty == 1'b1) ? 1'b0 : (RD == 1'b0) ? 1'b0 : 1'b1;
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- assign n_add_RD = (add_RD) + 4'h1;
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+ assign n_add_RD = add_RD + 4'h1;
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always @(posedge clk_RD, posedge rst) begin
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if((rst == 1'b1)) begin
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add_RD <= {5{1'b0}};
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diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/test.v temp/verilog/test.v
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--- a/translated_examples/test.v 1970-01-01 00:00:01.000000000 +0000
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+++ a/temp/verilog/test.v 2022-05-11 03:44:43.189604945 +0000
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@@ -125,7 +125,7 @@
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endcase
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end
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- assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
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+ assign code1[1:0] = a[6:5] ^ {a[4],b[6]};
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// Asynch process
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always @(we, addr, config1, bip) begin
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if(we == 1'b1) begin
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diff -u '--exclude=Makefile' '--exclude-from=examples/exclude' translated_examples/withselect.v temp/verilog/withselect.v
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--- a/translated_examples/withselect.v 1970-01-01 00:00:01.000000000 +0000
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+++ a/temp/verilog/withselect.v 2022-05-11 03:44:43.193604945 +0000
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@@ -33,7 +33,7 @@
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endcase
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end
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- assign code1[1:0] = a[6:5] ^ ({a[4],b[6]});
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+ assign code1[1:0] = a[6:5] ^ {a[4],b[6]};
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assign foo = {(((1 + 1))-((0))+1){1'b0}};
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assign egg = {78{1'b0}};
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assign baz = {(((bus_width * 4))-((bus_width * 3 - 1))+1){1'b1}};
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