vhd2vl: fix compatibility with verilog 11.0

pkgs/applications/science/electronics/vhd2vl/default.nix

@@ -1,5 +1,6 @@
 { stdenv
 , fetchFromGitHub
+, fetchpatch
 , bison
 , flex
 , verilog
@@ -16,6 +17,15 @@ stdenv.mkDerivation rec {
     sha256 = "17va2pil4938j8c93anhy45zzgnvq3k71a7glj02synfrsv6fs8n";
   };
 
+  patches = stdenv.lib.optionals (!stdenv.isAarch64) [
+    # fix build with verilog 11.0 - https://github.com/ldoolitt/vhd2vl/pull/15
+    # for some strange reason, this is not needed for aarch64
+    (fetchpatch {
+      url = "https://github.com/ldoolitt/vhd2vl/commit/ce9b8343ffd004dfe8779a309f4b5a594dbec45e.patch";
+      sha256 = "1qaqhm2mk66spb2dir9n91b385rarglc067js1g6pcg8mg5v3hhf";
+    })
+  ];
+
   nativeBuildInputs = [
     bison
     flex