Log: ``` patching sources applying patch /nix/store/6m27y27zvzsjn1ir4y8mm9nc9xnh2sgx-riscv-no-relax.patch patching file gcc/config/riscv/riscv.c Reversed (or previously applied) patch detected! Assume -R? [n] Apply anyway? [n] Skipping patch. 1 out of 1 hunk ignored -- saving rejects to file gcc/config/riscv/riscv.c.rej patching file gcc/config/riscv/riscv.opt Reversed (or previously applied) patch detected! Assume -R? [n] Apply anyway? [n] Skipping patch. 1 out of 1 hunk ignored -- saving rejects to file gcc/config/riscv/riscv.opt.rej patching file gcc/doc/invoke.texi Reversed (or previously applied) patch detected! Assume -R? [n] Apply anyway? [n] Skipping patch. ```wip/yesman
Patrick Hilhorst
6 years ago
parent
728eb27618
commit
d0708a30c4
@ -1,109 +0,0 @@ |
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commit e7c570f37384d824cb9725f237920e9691e57269
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gpg: Signature made Tue 06 Mar 2018 04:52:46 PM PST
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gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
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gpg: issuer "palmer@dabbelt.com"
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gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [ultimate]
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gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [ultimate]
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Author: Palmer Dabbelt <palmer@sifive.com>
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Date: Thu Mar 1 12:01:06 2018 -0800
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RISC-V: Add and document the "-mno-relax" option
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RISC-V relies on aggressive linker relaxation to get good code size. As
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a result no text symbol addresses can be known until link time, which
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means that alignment must be handled during the link. This alignment
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pass is essentially just another linker relaxation, so this has the
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unfortunate side effect that linker relaxation is required for
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correctness on many RISC-V targets.
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The RISC-V assembler has supported an ".option norelax" for a long time
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because there are situations in which linker relaxation is a bad idea --
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the canonical example is when trying to materialize the initial value of
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the global pointer into a register, which would otherwise be relaxed to
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a NOP. We've been relying on users who want to disable relaxation for
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an entire link to pass "-Wl,--no-relax", but that still relies on the
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linker relaxing R_RISCV_ALIGN to handle alignment despite it not being
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strictly necessary.
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This patch adds a GCC option, "-mno-relax", that disable linker
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relaxation by adding ".option norelax" to the top of every generated
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assembly file. The assembler is smart enough to handle alignment at
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assemble time for files that have never emitted a relaxable relocation,
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so this is sufficient to really disable all relaxations in the linker,
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which results in significantly faster link times for large objects.
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This also has the side effect of allowing toolchains that don't support
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linker relaxation (LLVM and the Linux module loader) to function
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correctly. Toolchains that don't support linker relaxation should
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default to "-mno-relax" and error when presented with any R_RISCV_ALIGN
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relocation as those need to be handled for correctness.
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gcc/ChangeLog
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2018-03-01 Palmer Dabbelt <palmer@sifive.com>
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* config/riscv/riscv.opt (mrelax): New option.
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* config/riscv/riscv.c (riscv_file_start): Emit ".option
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"norelax" when riscv_mrelax is disabled.
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* doc/invoke.texi (RISC-V): Document "-mrelax" and "-mno-relax".
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diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
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index c38f6c394d54..3e81874de232 100644
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--- a/gcc/config/riscv/riscv.c
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+++ b/gcc/config/riscv/riscv.c
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@@ -3979,6 +3979,11 @@ riscv_file_start (void)
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/* Instruct GAS to generate position-[in]dependent code. */
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fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no"));
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+
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+ /* If the user specifies "-mno-relax" on the command line then disable linker
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+ relaxation in the assembler. */
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+ if (! riscv_mrelax)
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+ fprintf (asm_out_file, "\t.option norelax\n");
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}
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/* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text
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diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
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index 581a26bb5c1e..b37ac75d9bb4 100644
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--- a/gcc/config/riscv/riscv.opt
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+++ b/gcc/config/riscv/riscv.opt
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@@ -106,6 +106,11 @@ mexplicit-relocs
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Target Report Mask(EXPLICIT_RELOCS)
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Use %reloc() operators, rather than assembly macros, to load addresses.
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+mrelax
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+Target Bool Var(riscv_mrelax) Init(1)
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+Take advantage of linker relaxations to reduce the number of instructions
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+required to materialize symbol addresses.
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+
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Mask(64BIT)
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Mask(MUL)
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diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
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index 8d366c626bae..deb48af2ecad 100644
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--- a/gcc/doc/invoke.texi
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+++ b/gcc/doc/invoke.texi
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@@ -1042,7 +1042,8 @@ See RS/6000 and PowerPC Options.
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-msave-restore -mno-save-restore @gol
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-mstrict-align -mno-strict-align @gol
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-mcmodel=medlow -mcmodel=medany @gol
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--mexplicit-relocs -mno-explicit-relocs @gol}
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+-mexplicit-relocs -mno-explicit-relocs @gol
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+-mrelax -mno-relax @gol}
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@emph{RL78 Options}
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@gccoptlist{-msim -mmul=none -mmul=g13 -mmul=g14 -mallregs @gol
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@@ -23102,6 +23103,12 @@ Use or do not use assembler relocation operators when dealing with symbolic
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addresses. The alternative is to use assembler macros instead, which may
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limit optimization.
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+@item -mrelax
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+@itemx -mno-relax
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+Take advantage of linker relaxations to reduce the number of instructions
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+required to materialize symbol addresses. The default is to take advantage of
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+linker relaxations.
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+
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@end table
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@node RL78 Options
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@ -1,13 +0,0 @@ |
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Index: gcc/config/riscv/linux.h
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===================================================================
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--- a/gcc/config/riscv/linux.h (revision 257620)
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+++ b/gcc/config/riscv/linux.h (revision 257621)
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@@ -47,6 +47,8 @@
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#define ICACHE_FLUSH_FUNC "__riscv_flush_icache"
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+#define CPP_SPEC "%{pthread:-D_REENTRANT}"
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+
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#define LINK_SPEC "\
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-melf" XLEN_SPEC "lriscv \
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%{shared} \
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