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283 lines
9.4 KiB
283 lines
9.4 KiB
diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
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index dd10cf78f2d3..8f006638452b 100644
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--- a/drivers/nvme/host/pci.c
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+++ b/drivers/nvme/host/pci.c
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@@ -28,8 +28,8 @@
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#include "trace.h"
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#include "nvme.h"
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-#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
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-#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
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+#define SQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_command))
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+#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
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#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
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@@ -1344,16 +1344,16 @@ static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
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static void nvme_free_queue(struct nvme_queue *nvmeq)
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{
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- dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth),
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+ dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
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(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
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if (!nvmeq->sq_cmds)
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return;
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if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
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pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
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- nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth));
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+ nvmeq->sq_cmds, SQ_SIZE(nvmeq));
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} else {
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- dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth),
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+ dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
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nvmeq->sq_cmds, nvmeq->sq_dma_addr);
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}
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}
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@@ -1433,12 +1433,12 @@ static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
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}
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static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
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- int qid, int depth)
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+ int qid)
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{
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
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- nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth));
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+ nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
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if (nvmeq->sq_cmds) {
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nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
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nvmeq->sq_cmds);
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@@ -1447,11 +1447,11 @@ static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
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return 0;
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}
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- pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(depth));
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+ pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
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}
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}
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- nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
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+ nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
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&nvmeq->sq_dma_addr, GFP_KERNEL);
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if (!nvmeq->sq_cmds)
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return -ENOMEM;
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@@ -1465,12 +1465,13 @@ static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
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if (dev->ctrl.queue_count > qid)
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return 0;
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- nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth),
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+ nvmeq->q_depth = depth;
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+ nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
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&nvmeq->cq_dma_addr, GFP_KERNEL);
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if (!nvmeq->cqes)
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goto free_nvmeq;
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- if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
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+ if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
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goto free_cqdma;
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nvmeq->dev = dev;
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@@ -1479,15 +1480,14 @@ static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
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nvmeq->cq_head = 0;
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nvmeq->cq_phase = 1;
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nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
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- nvmeq->q_depth = depth;
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nvmeq->qid = qid;
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dev->ctrl.queue_count++;
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return 0;
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free_cqdma:
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- dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
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- nvmeq->cq_dma_addr);
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+ dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
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+ nvmeq->cq_dma_addr);
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free_nvmeq:
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return -ENOMEM;
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}
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@@ -1515,7 +1515,7 @@ static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
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nvmeq->cq_head = 0;
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nvmeq->cq_phase = 1;
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nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
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- memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
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+ memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
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nvme_dbbuf_init(dev, nvmeq, qid);
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dev->online_queues++;
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wmb(); /* ensure the first interrupt sees the initialization */
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diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
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index cc09b81fc7f4..716ebe87a2b8 100644
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--- a/drivers/nvme/host/core.c
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+++ b/drivers/nvme/host/core.c
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@@ -1986,6 +1986,7 @@ int nvme_enable_ctrl(struct nvme_ctrl *ctrl, u64 cap)
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ctrl->ctrl_config = NVME_CC_CSS_NVM;
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ctrl->ctrl_config |= (page_shift - 12) << NVME_CC_MPS_SHIFT;
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ctrl->ctrl_config |= NVME_CC_AMS_RR | NVME_CC_SHN_NONE;
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+ /* Use default IOSQES. We'll update it later if needed */
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ctrl->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
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ctrl->ctrl_config |= NVME_CC_ENABLE;
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@@ -2698,6 +2699,30 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
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ctrl->hmmin = le32_to_cpu(id->hmmin);
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ctrl->hmminds = le32_to_cpu(id->hmminds);
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ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
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+
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+ /* Grab required IO queue size */
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+ ctrl->iosqes = id->sqes & 0xf;
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+ if (ctrl->iosqes < NVME_NVM_IOSQES) {
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+ dev_err(ctrl->device,
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+ "unsupported required IO queue size %d\n", ctrl->iosqes);
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+ ret = -EINVAL;
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+ goto out_free;
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+ }
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+ /*
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+ * If our IO queue size isn't the default, update the setting
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+ * in CC:IOSQES.
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+ */
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+ if (ctrl->iosqes != NVME_NVM_IOSQES) {
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+ ctrl->ctrl_config &= ~(0xfu << NVME_CC_IOSQES_SHIFT);
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+ ctrl->ctrl_config |= ctrl->iosqes << NVME_CC_IOSQES_SHIFT;
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+ ret = ctrl->ops->reg_write32(ctrl, NVME_REG_CC,
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+ ctrl->ctrl_config);
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+ if (ret) {
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+ dev_err(ctrl->device,
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+ "error updating CC register\n");
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+ goto out_free;
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+ }
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+ }
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}
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ret = nvme_mpath_init(ctrl, id);
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diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
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index 716a876119c8..34ef35fcd8a5 100644
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--- a/drivers/nvme/host/nvme.h
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+++ b/drivers/nvme/host/nvme.h
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@@ -244,6 +244,7 @@ struct nvme_ctrl {
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u32 hmmin;
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u32 hmminds;
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u16 hmmaxd;
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+ u8 iosqes;
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/* Fabrics only */
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u16 sqsize;
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diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
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index 8f006638452b..54b35ea4af88 100644
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--- a/drivers/nvme/host/pci.c
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+++ b/drivers/nvme/host/pci.c
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@@ -28,7 +28,7 @@
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#include "trace.h"
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#include "nvme.h"
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-#define SQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_command))
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+#define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
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#define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
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#define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
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@@ -162,7 +162,7 @@ static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
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struct nvme_queue {
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struct nvme_dev *dev;
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spinlock_t sq_lock;
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- struct nvme_command *sq_cmds;
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+ void *sq_cmds;
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/* only used for poll queues: */
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spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
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volatile struct nvme_completion *cqes;
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@@ -178,6 +178,7 @@ struct nvme_queue {
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u16 last_cq_head;
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u16 qid;
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u8 cq_phase;
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+ u8 sqes;
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unsigned long flags;
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#define NVMEQ_ENABLED 0
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#define NVMEQ_SQ_CMB 1
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@@ -488,7 +489,8 @@ static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
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bool write_sq)
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{
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spin_lock(&nvmeq->sq_lock);
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- memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
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+ memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
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+ cmd, sizeof(*cmd));
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if (++nvmeq->sq_tail == nvmeq->q_depth)
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nvmeq->sq_tail = 0;
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nvme_write_sq_db(nvmeq, write_sq);
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@@ -1465,6 +1467,7 @@ static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
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if (dev->ctrl.queue_count > qid)
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return 0;
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+ nvmeq->sqes = qid ? dev->ctrl.iosqes : NVME_NVM_ADMSQES;
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nvmeq->q_depth = depth;
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nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
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&nvmeq->cq_dma_addr, GFP_KERNEL);
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diff --git a/include/linux/nvme.h b/include/linux/nvme.h
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index 01aa6a6c241d..7af18965fb57 100644
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--- a/include/linux/nvme.h
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+++ b/include/linux/nvme.h
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@@ -141,6 +141,7 @@ enum {
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* (In bytes and specified as a power of two (2^n)).
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*/
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#define NVME_NVM_IOSQES 6
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+#define NVME_NVM_ADMSQES 6
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#define NVME_NVM_IOCQES 4
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enum {
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diff --git a/drivers/nvme/host/core.c b/drivers/nvme/host/core.c
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index 716ebe87a2b8..480ea24d8cf4 100644
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--- a/drivers/nvme/host/core.c
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+++ b/drivers/nvme/host/core.c
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@@ -2701,7 +2701,10 @@ int nvme_init_identify(struct nvme_ctrl *ctrl)
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ctrl->hmmaxd = le16_to_cpu(id->hmmaxd);
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/* Grab required IO queue size */
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- ctrl->iosqes = id->sqes & 0xf;
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+ if (ctrl->quirks & NVME_QUIRK_128_BYTES_SQES)
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+ ctrl->iosqes = 7;
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+ else
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+ ctrl->iosqes = id->sqes & 0xf;
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if (ctrl->iosqes < NVME_NVM_IOSQES) {
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dev_err(ctrl->device,
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"unsupported required IO queue size %d\n", ctrl->iosqes);
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diff --git a/drivers/nvme/host/nvme.h b/drivers/nvme/host/nvme.h
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index 34ef35fcd8a5..b2a78d08b984 100644
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--- a/drivers/nvme/host/nvme.h
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+++ b/drivers/nvme/host/nvme.h
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@@ -92,6 +92,16 @@ enum nvme_quirks {
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* Broken Write Zeroes.
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*/
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NVME_QUIRK_DISABLE_WRITE_ZEROES = (1 << 9),
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+
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+ /*
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+ * Use only one interrupt vector for all queues
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+ */
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+ NVME_QUIRK_SINGLE_VECTOR = (1 << 10),
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+
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+ /*
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+ * Use non-standard 128 bytes SQEs.
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+ */
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+ NVME_QUIRK_128_BYTES_SQES = (1 << 11),
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};
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/*
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diff --git a/drivers/nvme/host/pci.c b/drivers/nvme/host/pci.c
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index 54b35ea4af88..ab2358137419 100644
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--- a/drivers/nvme/host/pci.c
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+++ b/drivers/nvme/host/pci.c
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@@ -2080,6 +2080,9 @@ static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
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dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
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dev->io_queues[HCTX_TYPE_READ] = 0;
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+ if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
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+ irq_queues = 1;
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+
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return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
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PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
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}
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@@ -3037,6 +3040,9 @@ static const struct pci_device_id nvme_id_table[] = {
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{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
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{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
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{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
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+ { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
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+ .driver_data = NVME_QUIRK_SINGLE_VECTOR |
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+ NVME_QUIRK_128_BYTES_SQES },
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{ 0, }
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};
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MODULE_DEVICE_TABLE(pci, nvme_id_table);
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